Generation working and Compilation of MARTe components

EC-GN-JA-PCF/.svn/pristine/f5/f54562cad53678797b8e28923d1b18b1d2816add.svn-base

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+#!/usr/bin/python
+
+import time
+import sys
+import subprocess
+
+import test_async
+import test_sync
+import test_ready_hw
+import test_setup_hw
+import test_standby_hw
+import test_ready
+import test_setup
+import test_standby
+import test_setup_rup_confirm
+
+#
+# Some EPICS PVs need to be simulation mode when we test code without PXI board.
+# When user uses sim mode, new value must be written into PV.SVAL and PV itselfself.
+#
+print '### Start State Machine Sequence Test ###'
+
+print '---------- Pre setup for the test ----------'
+test_setup_rup_confirm.test_setup()
+#test_setup.test_setup()
+#test_setup_hw.test_setup()
+
+