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Added custom changes EPICs fast boards drivers

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This commit is contained in:
ferrog
2025-05-15 15:10:34 +00:00
parent 01dae2f39b
commit 13772b30aa
13 changed files with 900 additions and 10 deletions
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64
patches/EC-GN-PCF0CORE_userPreDriverConf.patch Normal file
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############################################################################
## User provided PLC or fast controller driver pre configuration
############################################################################
### PXIe-6368 setup
## AO Port ##
asynXseriesResetAoConfiguration("ni6368_0")
asynXseriesStaticAo("ni6368_0")
asynXseriesAddAoChannel("ni6368_0", 0, 0)
asynXseriesAddAoChannel("ni6368_0", 1, 0)
asynXseriesAddAoChannel("ni6368_0", 2, 0)
asynXseriesAddAoChannel("ni6368_0", 3, 0)
asynXseriesLoadAoConfiguration("ni6368_0")
asynXseriesStartAo("ni6368_0")
asynXseriesResetAoConfiguration("ni6368_1")
asynXseriesStaticAo("ni6368_1")
asynXseriesAddAoChannel("ni6368_1", 0, 0)
asynXseriesAddAoChannel("ni6368_1", 1, 0)
asynXseriesAddAoChannel("ni6368_1", 2, 0)
asynXseriesAddAoChannel("ni6368_1", 3, 0)
asynXseriesLoadAoConfiguration("ni6368_1")
asynXseriesStartAo("ni6368_1")
## AI Port ##
### PXI-6259 setup
pxi6259_ai_start_trig(0, 1, 0, 0) #boardnumber, enable, trigger_source, trigger_edge
pxi6259_ai_start_trig(1, 1, 0, 0) #boardnumber, enable, trigger_source, trigger_edge
### PXI-6528 setup
### set change detection to both
pxi6528_set_port_change_detection("ni6528_0", 0, 255, 255)
pxi6528_set_port_change_detection("ni6528_0", 1, 255, 255)
pxi6528_set_port_change_detection("ni6528_0", 2, 255, 255)
pxi6528_set_port_change_detection("ni6528_1", 0, 255, 255)
pxi6528_set_port_change_detection("ni6528_1", 1, 255, 255)
pxi6528_set_port_change_detection("ni6528_1", 2, 255, 255)
### enable IO intr mode
pxi6528_enable_io_intr_scanning("ni6528_0")
pxi6528_enable_io_intr_scanning("ni6528_1")
### Stream Device setup ####################################
### set appropriate IP address and port number
drvAsynIPPortConfigure("CCPS1", "192.168.5.2:5025")
drvAsynIPPortConfigure("FHPS1", "192.168.5.3:6000")
drvAsynIPPortConfigure("MC1", "192.168.5.4:6000")
drvAsynIPPortConfigure("GC1", "192.168.5.5:6000")
drvAsynIPPortConfigure("CCPS2", "192.168.5.6:5025")
drvAsynIPPortConfigure("FHPS2", "192.168.5.7:6000")
drvAsynIPPortConfigure("MC2", "192.168.5.8:6000")
drvAsynIPPortConfigure("GC2", "192.168.5.9:6000")