added dummy signal

2026-02-06 17:27:21 +01:00
1 parent 25e7daf7e4
commit 0177b52b7f
@@ -345,10 +345,14 @@
    PLC_SYNCMODE = {
      Type = uint8
    }
-    //# DI.21
+    //# DI.22
    TRIGGER = {
      Type = uint8
    }
+    //# DI.23
+    NONE_DI23 = {
+      Type = uint8
+    }
    //# DO.0
    APS_HVON = {
      Type = uint8
@@ -85,6 +85,9 @@
    TRIGGER = {
      DataSource = DDB3
    }
+    NONE_DI23 = {
+      DataSource = DDB3
+    }
  }
 }
 // Digital Output port access.