added dummy signal

This commit is contained in:
Martino Ferrari committed 2026-02-06 17:27:21 +01:00
1 parent 25e7daf7e4
commit 0177b52b7f
2 files changed
+8 -1

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@@ -345,10 +345,14 @@
PLC_SYNCMODE = { PLC_SYNCMODE = {
Type = uint8 Type = uint8
} }
//# DI.21 //# DI.22
TRIGGER = { TRIGGER = {
Type = uint8 Type = uint8
} }
//# DI.23
NONE_DI23 = {
Type = uint8
}
//# DO.0 //# DO.0
APS_HVON = { APS_HVON = {
Type = uint8 Type = uint8
@@ -85,6 +85,9 @@
TRIGGER = { TRIGGER = {
DataSource = DDB3 DataSource = DDB3
} }
NONE_DI23 = {
DataSource = DDB3
}
} }
} }
// Digital Output port access. // Digital Output port access.